This invention relates to integrated circuits, and more particularly to the routing of boundary scan control conductors to control boundary scan cells associated with the integrated circuit input/output pads.
The use of boundary scan chains to input data into integrated circuits, test integrated circuits and test systems of integrated circuits has become ubiquitous. EEE standard 1149.1, and revisions thereto, each of which is hereby incorporated by reference, often referred to as JTAG, defines the logic for implementing a boundary scan chain. U.S. Pat. No. 5,355,369 discloses a high speed integrated circuit that provides for boundary scan testing, the disclosure of which is hereby incorporated by reference. A boundary scan chain is comprised of cells of logic at each input/output path. The input/output paths are typically located around the periphery of an integrated circuit die. The logic cells, also known as boundary scan cells, are controlled in accordance with the above-mentioned standard by control signals. The control signals are typically provided to each boundary scan cell by a xe2x80x9cringxe2x80x9d bus proximate the boundary scan cells, with each ring bus conductor being endless, that is forming a loop, and driven at a single point. Data is transferred sequentially from one boundary scan cell to an adjacent boundary scan cell. Thus data is shifted from any boundary scan cell to an adjacent boundary scan cell in the same manner data is shifted from a register in a shift register to the next register in the shift register.
A problem that arises with the ring implementation of the control signal conductors is the potential for a race condition. The race condition occurs when transferring data between two adjacent latches. One of the adjacent latches is the output latch of a boundary scan cell from which data is being transferred and the other of the adjacent latches is the input latch of the adjacent boundary scan cell into which data is being shifted. A race condition exists if the skew introduced in the clock control signal between the two adjacent latches is greater than the propagation delay to transfer data from one of the two adjacent latches to the other.
One technique to overcome the potential race condition is to break the ring bus conductor to which the clock signal is applied. The ring bus conductor is broken between the first boundary scan cell and the last boundary scan cell in the boundary scan chain. The clock signal drives an end of the broken clock ring bus conductor such that the clock signal propagates around the broken ring in the opposite direction that data is shifted through adjacent boundary scan cells. In this manner, data is shifted around the sequence of boundary scan cells in one direction, for example counter clockwise, while the clock signal propagates around the broken clock ring bus conductor in the opposite direction, for example clockwise, or vice versa.
While this technique resolves the race condition described above, another potential race condition is introduced by breaking the clock ring bus conductor and driving an end of the broken clock ring bus conductor. The potential race condition introduced occurs at the first boundary scan cell to receive data. The first boundary scan cell receives the clock signal with the greatest skew since the clock signal travels the greatest distance to arrive at the first boundary scan cell. When the active low shift signal goes low, the data being shifted into the first boundary scan cell passes through the first, master, latch and is latched in a second, slave, latch when the shift signal arrives at the first boundary scan cell before the clock signal arrives (a late clock condition) at the first boundary scan cell.
What is needed is a technique to overcome the potential race condition, introduced in the ring bus configuration, due to clock skew being greater than the propagation delay to transfer data from one of two adjacent latches to the other, without introducing other potential race conditions.
In accordance with the invention, an integrated circuit includes a semiconductor die having a plurality of input/output pads. A plurality of boundary scan cells, one corresponding to each input/output pad, implements boundary scan functions associated with respective input/output pads. Each of the boundary scan cells includes a TDI input and a TDO output. The boundary scan cells are structured as a shift register to shift data from one boundary scan cell in a direction unilaterally to an adjacent boundary scan cell. A first boundary scan cell is the first boundary scan cell of the plurality of boundary scan cells to receive data. A last boundary scan cell is the last boundary scan cell of the plurality of boundary scan cells to receive data. An endless control conductor forms a loop proximate the plurality of boundary scan cells. The endless control conductor is coupled to each of the plurality of boundary scan cells to provide a test clock signal thereto. At least one other control conductor extends around the semiconductor die proximate the plurality of boundary scan cells. The at least one other control conductor is coupled to each of the plurality of boundary scan cells and is discontinuous between the first and last boundary scan cells. The invention may also be implemented at a system level.